The present invention relates to an active-matrix liquid crystal display (hereinafter may be referred to as "ANLCD") of the type integrally formed with driver circuitry which employs thin film transistors (hereinafter may be referred to as "TFTs") as pixel switching elements and CMOS driver circuit transistors, and to a fabrication method therefor.
FIGS. 11(a) to 11(g) are sectional views for illustrating a method for fabricating a CMOS driver circuit and a TFT of offset structure as a pixel switching element. This method utilizes a conventional CMOS driver circuit fabrication method as disclosed in, for example, Japanese Unexamined Patent Publication No. 286368/1992 and an offset TFT fabrication method as disclosed in Japanese Unexamined Patent Publication No. 275450/1993. In FIGS. 11(a) to 11(g), numeral 1 denotes an insulative substrate, numeral 2 a polysilicon film for use as a channel semiconductor film, numeral 3 a gate insulating film, numeral 4 an n.sup.+ -polysilicon containing phosphorus (hereinafter represented as P) at a high concentration and intended for a gate electrode, numerals 5a, 5b, 5c, 5d, 5e, 5f and 5g photoresists, numerals 16 and 26 n.sup.+ -polysilicon layers implanted with P ion at a high concentration and intended for source/drain regions, and numerals 27 and 37 p.sup.+ -polysilicon layers implanted with boron (hereinafter represented as B) ion at a high concentration. An n-channel TFT 10 as a pixel switching element herein shown is of offset structure, while n- and p-channel TFTs forming a CMOS driver circuit are not of offset structure but of typical planar structure.
The TFTs of the aforementioned structure are fabricated by the following method. The semiconductor polysilicon film 2 to be used as a channel is formed on the insulative substrate 1, followed by forming the photoresist 5a (refer to FIG. 11(a)) and patterning the polysilicon film 2 to define islands for TFTs. The gate insulating film 3 is then formed by a thermal oxidation process or a same process (refer to FIG. 11(b)).
In turn, the n.sup.+ -polysilicon film 4 is formed (refer to FIG. 11(c)).
In turn, as shown in FIG. 11(d), a gate electrode pattern of photoresist 5b is formed only on the island intended for TFT 10 for use in a switching element of the pixel portion (that may be hereinafter referred to as the pixel switching TFT). At this time, the islands intended for the CMOS driver TFTs are entirely covered with the photoresist 5c and are not patterned. To make the offset structure, a gate electrode with eaves shown in FIG. 11(d) is formed by overetching of the n.sup.+ -polysilicon, which is followed by dry-etching of the n.sup.+ -polysilicon film in the thicknesswise direction thereof by using SF.sub.6 gas or the like. Subsequently P is ion-implanted to the resulting substrate surface to form the n.sup.+ -polysilicon 16 heavily doped with P. In this case, the portion below the eaves of photoresist is not ion-implanted and, hence, the offset structure is realized.
After the photoresists 5b, 5c have been exfoliated, the photoresist 5d is formed for the formation of gate electrodes of the CMOS driver circuit, and then the n.sup.+ -polysilicon film is etched to form the gate electrodes 24, 34, as shown in FIG. 11(e). At this time, the pixel switching TFT 10 of offset structure is covered with the photoresist 5e. After the formation of the gate electrodes, B-ion implantation is carried out to form source/drain regions 27, 37 of p.sup.+ -polysilicon heavily doped with B. Thus, p-type TFT 30 is realized.
In turn, as shown in FIG. 11(f), after the pixel switching TFT 10 of offset structure and the p-type TFT 30 of the CMOS driver circuit are covered with photoresists 5f and 5g, respectively, P-ion implantation is carried out to a high concentration to form source/drain regions 26 of n.sup.+ -polysilicon. Thus, n-type TFT 20 of the CMOS driver circuit is fabricated.
The photoresists 5f, 5g are then exfoliated to realize the basic structure comprising the polysilicon TFT of offset structure to be used as the pixel switching element and the CMOS driver circuit, followed by the formation of source/drain electrodes.
Reference is then made to the operation of the thus formed structure. As described above, the polysilicon TFT of offset structure is used as the pixel switching element. A decrease in "OFF current" is of importance for the pixel switching element. Typically, it is desirable to decrease the "OFF current" to about 10.sup.-11 A or below. However, crystal defects present at the grain boundary influence the polysilicon TFT in the "OFF state" to make field emission current to flow in the drain region thereof, thereby increasing the "OFF current". Accordingly, it is difficult to decrease the "OFF current" to the aforementioned value. For this reason, offset regions are provided on opposite sides of the gate electrode as shown in FIGS. 11(d) to 11(g) so as to decrease the electric field of the drain region thereby to decrease the OFF current.
On the other hand, the CMOS driver circuit region allows an "OFF current" of up to about 10.sup.-9 A. Nevertheless, to realize a high speed operation, a high field effect mobility (i.e., high "ON current") is required. Since an offset region of a TFT serves as series resistance when the TFT is in the "ON state", the field effect mobility is lowered thereby. Therefore, the CMOS circuit employs polysilicon TFTs of the conventional planar type, not of the offset structure.
In constructing the basic TFT structure shown in FIGS. 11(d) to 11(g) comprising the pixel switching TFT of offset structure and the CMOS driver circuit according to the conventional method, the photolithographic process is required to be carried out at least three times and the dry etching process at least three times. This results in a lengthy production process. Further, since the CMOS driver circuit comprises the conventional planar TFTs, higher power source voltage causes a higher electric field to be applied to the drain region of TFT and, hence, a problem of extremely increased drain current will result. For this reason, the power source voltage to be applied to the CMOS transistors is restricted to at most 20 V. This also restricts the gate voltage and source voltage of the pixel switching TFT in driving the liquid crystal.
The present invention has been attained to overcome the foregoing problems. It is, therefore, an object of the present invention to provide an active-matrix liquid crystal display integrally formed with a driver circuit which includes TFTs fabricated on one of a pair of substrates in a shortened process and a CMOS driver circuit adaptable for a high power voltage.
Another object of the present invention is to provide a method for fabricating such an active-matrix liquid crystal display.